1. Field of the Invention
The present invention relates to flash semiconductor memory, and more particularly to small sector floating gate flash memory having hot electron programming and Fowler-Nordheim erase.
2. Description of the Related Art
One common type of floating gate flash memory uses channel hot electron (“CHE”) injection for programming the floating gate memory cells, and Fowler-Nordheim (“FN”) tunneling for erasing the memory cells. Because of small cell size, fast read speed, and good program/erase endurance, floating gate type flash memory is widely used for code storage applications in mobile devices, PC BIOS, and many consumer devices. Floating gate flash memories typically have large sector sizes. FIG. 1 shows an illustrative 4M bit flash memory array that is organized into 2048 programmable pages of 256-bytes each. The pages are grouped into 8 erasable sectors of 256 pages each. The sector size therefore is 64 Kbytes.
Another common type of memory is the split gate flash memory. Split gate flash memory tends to be well suited to data storage because its erasable sectors are small, and many data storage applications involve the transfer of small amounts of bytes. The split-gate flash memory may be designed with a sector size for the Erase operation that is much smaller than that typically used for the floating gate flash memory. A typical sector for split gate flash memory ranges from about 4K bytes to about 256 bytes, compared to 64K bytes for floating gate flash memory.
The reason for the relatively large sector size in floating gate flash memory has to do with the need for sector isolation. In conventional floating gate flash memory, the cells in the same sector typically are deployed in the same P-well and are isolated from cells of other sectors by sector select transistors. The overhead imposed by separate P-wells and the use of respective groups of select transistors for the sectors can result in a big die size penalty if small sectors are implemented. For a 4M-bit flash memory array, for example, the overhead is on the order of a one percent increase in die size to implement one P well separation and sufficient sector select transistors to create the sector. Compared to a bulk mode flash memory in which all cells of the array are erased together, a 4 M-bit flash memory having large P-wells respectively containing sectors of 64 Kbytes has an 8% die size penalty, while the same size flash memory having more small P-wells respectively containing sectors of 4 Kbytes has a 108% die size penalty.
If multiple sectors of cells are deployed within a single P-well without any supplemental P-well isolation structures, the die size penalty is reduced. However, when multiple sectors are created within a particular P-well, and as cells in the particular P-well are programmed or erased by selecting various rows and sectors of cells in the particular P-well over time, the cells in the particular P-well that are not frequently selected suffer from programming disturb and erase disturb. In view of the importance of minimizing the die size penalty, techniques have been developed which allow cells to be disturbed but which correct the disturbed cells by refreshing or reprogramming them.
One refresh procedure for correcting disturb conditions is disclosed in U.S. Pat. No. 6,166,959, issued Dec. 26, 2000 to Gupta et al. This refresh procedure involves uploading the contents of a Refresh area to an internal RAM, and then downloading the data back to the Refresh area. Specifically, an internal refresh periodically rewrites the information stored in each of the rows of memory cells in a flash memory. The flash memory array includes a refresh pointer bitline that indicates the row to be refreshed. In a first embodiment, the internal refresh is performed automatically after every user erase/program cycle. In second and third embodiments, the user of the of the flash memory array selects when the internal refresh is performed, but the address of the row to be refreshed is supplied internally. In each of the three the embodiments, the internal refresh includes the four operations of Scan, Refresh Erase, Refresh Program, and Increment. Disadvantageously, the internal RAM imposes an overhead expense, and the refresh time tends to be long because of the large number of cells in the Refresh area that are refreshed.
Another refresh procedure for correcting disturb conditions is disclosed in U.S. Pat. No. 6,005,810, issued Dec. 21, 1999 to Wu. A byte-programmable/byte-erasable flash memory system is provided with on-chip counters and secondary storage. The counters count the numbers of program/erase cycles and compare them with empirically pre-determined counter limits. When the program/erase count exceeds the counter limit, the data then carried in the system are temporarily transferred onto the secondary storage while the memory array is refreshed and the counters are reset.
Another refresh procedure for correcting disturb conditions is disclosed in U.S. Pat. No. 6,668,303, issued Dec. 23, 2003 to Pio. This refresh procedure involves detecting the memory cells within a sector whose datum has been partially lost, and reprogramming the datum in the detected cells. The process of detecting partial data loss involves reading the memory cells in the sector using two different read voltages, a standard read voltage and a margin read voltage. The standard reading tells whether the cell is erased or programmed. The margin read, which involves more critical sensing conditions, tells whether the programmed cell has lost enough charge so that it should be refresh. While total refresh time is improved over the time required by the refresh procedure of the '959 patent because only the cells which have lost significant charge must be reprogrammed, the refresh procedure has a number of other disadvantageous. In one implementation, the refresh time is lengthy because two read operation per cell must be performed in the refresh area with different bias conditions. While this problem is avoided in another implementation by the use of two sense amplifiers per bit, this doubling of the number of sense amplifiers increases both the die size and power overhead.
Since existing refresh procedures for floating gate flash memory have disadvantages, there is need for improved control of disturb conditions in floating gate flash memories having hot electron programming and Fowler-Nordheim erase.